1. Field of the Invention
The present invention relates to a layer allocating apparatus for a multi-layer circuit board, and more particularly, to a layer allocating apparatus having reference ground areas formed on the power layers, so as to allow signal layout areas of solder layers to take reference to the reference grounding areas of the power layer to which the solder layer is adjacent, thereby improving the signal transmission quality of the solder layer to the same level the component layer pertains. Still, the present invention discloses a layer allocating apparatus with an enlargeable area for each power layer, which is obtained by setting vias to electrically couple with corresponding power planes of component layers, power layers, and solder layers, so as to have a stable power source and attenuate the ground/bounce effect simultaneously.
2. Description of the Prior Art
Recently, the four-layer circuit board has gradually replaced the six-layer counterpart to become the most widely used circuit board apparatus. Basically speaking, the four-layer circuit board is arranged from top to bottom as follows: component layer, ground layer, power layer, and solder layer. Among these layers of different purposes, the component layer is for placing the integrated circuitry and the primary part of signal lines, and the ground layer consists of a complete and slicing-free copper foil for connecting to the ground voltage. Besides, the power layer further includes a plurality of areas each stands for a power plane to provide different voltage levels to different components. The solder layer includes solder balls for soldering with other circuit boards and has some non-critical signals, such as memory address signals and control signals, arranged thereon. However, those critical signals, such as address strobe signals, data strobe signals, timing signals should be located in the component layer because they must be transmitted under a circumstance having better signal transmission quality.
Please refer to FIG. 1 of a schematic diagram of a layer allocating apparatus based on the prior art, wherein the motherboard and the circuit board is illustrated on a four-layer stacking apparatus basis, and the mother board upholds the circuit board, integrated circuit component 164, and other integrated circuit components such as 64A and 64B. The stacking apparatus 62 of motherboard is arranged as a component layer 65, a ground layer 66, a power layer 67, and a solder layer 68, from top to bottom in this order. The component layer 65 includes many other components, such as the integrated circuit component 164, and the signal line layout for connecting electrically with these components. Additionally, some other signal lines are placed on the solder layer 68. The same four-layer stacking apparatus 63A applies to the circuit board having a component layer 165A, a ground layer 166A, a power layer 167A, and a solder layer 168A, from top to bottom as well as the circuit board stacking apparatus 63B, which includes a component layer 165B, a ground layer 166B, a power layer 167B, and a solder layer 168B. For example, as signals transmitted from the integrated circuit component 64A to another integrated circuit component 64B first pass to the component layer 165A, then the ground layer 166A, the power layer 167A, the solder layer 168A, and via 69A of the solder layer 168A, so as to couple with the component layer 65 of the motherboard stacking apparatus 62. Thereafter, signals go through the via 69B of the target circuit board stacking apparatus 63B, the solder layer 168B, the power layer 167B, the ground layer 166B, and the component layer 165B, to reach the integrated circuit component 64B.
Please refer to FIG. 2 of a schematic diagram illustrating how the prior art power layer is arranged. The purpose of slicing the power layer into several power planes is to supply different operating voltages to different components. As shown in FIG. 2, the power layer includes a plurality of power planes 11, 12, 13, 14, 15, and 16, each of which is isolated from the others by the isolated line 21, for the sake of preventing interferences. Besides, each of these power planes includes a plurality of vias 22 for electrically coupling the component layer 165A and the solder layer 168A, so as to provide operating voltages with components placed thereon. With different operating voltage requirements, these power planes 11, 12, 13, 14, 15, and 16 are configured to provide different voltages. Taking the north bridge chip of the chipset for example, due to the north bridge chip is connected with the CPU, the memory, the south bridge chip, and the AGP device, power planes 12, 13, 14, and 15 provide different operating voltages respectively to meet the needs of CPU, memory, south bridge chip, and AGP device. Meanwhile, the voltage provided by the power plane 11 depends on if the north bridge chip supports any graphic device, and the remaining power plane 16 serves to be a ground voltage area. Therefore, as signals transmit between the north bridge chip and the CPU, memory, south bridge chip, or AGP device, these configured power planes each provides different voltages are viable.
As the integrated circuitry becomes more and more complicated and frequency demands become increasingly higher and higher, providing powers only through the power layer is not going to satisfy the requirement, because the current providing capabilities of these sliced power planes are limited, which is the consequence of limited plane size after the power layer is sliced for the sake of supplying different powers. Under this circumstance, the power plane ultimately generates a significant amount of ground/bounce effect, leading to unstable high-frequency signals and further resulting in malfunction of the whole system. While the distribution of vias become more and more concentrated, but the pitch between adjacent two signal lines, generally ranging from 3 to 5 mms inside a single chip, poises a constraint when it comes to arranging these vias. Currents provided by a small amount of vias may not provide enough connections with the power layer and components, causing these currents more and more unstable. Additionally, the critical signals are usually located in the component layer instead of in the solder layer, which significantly constrains design flexibility for designers.
The primary objective of the present invention is to disclose a layer allocating apparatus, which provides reference ground areas on the power layer, so as to allow signal lines of the solder layer to take reference to some reference ground areas of the power plane to which the solder layer is adjacent. Thereby, the signal transmission quality of the solder layer is supposed to be substantially equivalent to that of the power layer.
Still another objective of the invention is to disclose a layer allocating apparatus having enlargeable power planes. For this purpose, vias are set to electrically couple corresponding power planes on the component layer and solder layer, increasing the total area of power planes, so as to become a stable power source and attenuate the ground/bounce effect.
In a preferred embodiment, which is a 4-layer stacking apparatus arranged from top to bottom as a component layer, a ground layer, a power layer, and a solder layer, wherein the power layer includes a plurality of reference ground areas each is set to be located according to a corresponding signal layout area on the solder layer. In this way, signal lines of the solder layer and component layer all take reference to reference voltages of the ground layer and power layer, resulting in the substantially equivalent signal transmission quality for the solder layer and component layer, so as being able to place some critical components on the solder layer and then release some other space on the component layer.
In other words, the present invention discloses the same layout for power planes on the corresponding areas of the component layer, power layer, and solder layer. Power planes of the component layer, power layer, and solder layer are further communicated with their counterparts on different layers through the setting of vias, thereby increasing the total power plane area to supply stable power sources and lower down the ground/bounce effect.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.